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IDT70125L55J Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT70125L55J Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 12 page 6.10 5 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1,2,4) ADDRESS DATAOUT tRC tOH PREVIOUS DATA VALID tAA tOH DATA VALID 2654 drw 05 tBDD (3,4) BUSYOUT NOTES: 1. Timing depends on which signal is aserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultanious read operations BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/ W = VIH, and the address is valid prior to other coincidental with CE transition Low. 6. R/ W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low. CE tACE tAOE tHZ tLZ tPD VALID DATA tPU 50% OE DATAOUT CURRENT ICC ISS 50% 2654 drw 06 (4) tLZ tHZ (1) (1) (4) (2) (2) TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5,6) |
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