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IDT70825S20PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT70825S20PF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 21 page 6.31 10 IDT70825S/L HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Flag Status Bit 0, (Bit 1) Functional Description 0 Clears Buffer Flag EOB1, (EOB2). 1 No change to the Buffer Flag.(2) NOTES: 3016 tbl 18 1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone or cleared. 2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0). End of buffer flag for Buffer #1 End of buffer flag for Buffer #2 15 0 MSB H H H H HH H H HH H H H 1 0 LSB I/O BITS H 3016 drw 12 NOTE: 1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. Buffer #1 flow control Buffer #2 flow control Counter Release (STOP Mode Only) 15 MSB LSB I/O BITS 0 H HH H H HH 4 3 2 1 0 HH H H 3016 drw 11 FLOW CONTROL REGISTER DESCRIPTION(1,2) CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION(1) 3016 tbl 17 FLOW CONTROL BITS Flow Control Bits Bit 1 & Bit 0 Mode (Bit 3 & Bit 2) Functional Description 00 BUFFER EOB1 (EOB2) is asserted (Active Low output) when the pointer matches the end address of Buffer CHAINING #1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1).(1,3) 01 STOP EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2). The address pointer will stop incrementing when it reaches the next address ( EOB address + 1), if CNTEN is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register. (1,2,4) 10 LINEAR EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2). The pointer keeps incrementing for further operations.(1) 11 MASK EOB1 (EOB2) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #2), although the flag status bits will be set. The pointer keeps incrementing for further operations. NOTES: 1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value. 2. CMD Flow Control bits are unchanged, the count does not continue advancement. 3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1. 4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise the flow control will remain in the STOP mode. CASE 6: FLAG STATUS REGISTER WRITE CONDITIONS(1) 3016 tbl 19 Flag Status Bit 0, (Bit 1) Functional Description 0 EOB1 (EOB2) flag has not been set, the Pointer has not reached the End of the Buffer. 1 EOB1 (EOB2) flag has been set, the Pointer has reached the End of the Buffer. CASE 7: FLAG STATUS REGISTER READ CONDITIONS NOTES: 1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state. 2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT2 operations. |
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