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IDT6178S15P Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT6178S15P Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 7 page 11.1 1 IDT6178S CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM MILITARY AND COMMERCIAL TEMPERATURE RANGE Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1994 ©1994 Integrated Device Technology, Inc. DSC-1059/2 CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM IDT6178S FEATURES: • High-speed Address to MATCH Valid time – Military: 12/15/20/25ns – Commercial: 10/12/15/20/25ns (max.) • High-speed Address Access time – Military: 12/15/20/25ns – Commercial: 10/12/15/20/25ns (max.) • Low-power consumption – IDT6178S Active: 300mW (typ.) • Produced with advanced CMOS high-performance technology • Input and output TTL-compatible • Standard 22-pin Plastic or Ceramic DIP, 24-pin SOJ • Military product 100% compliant to MIL-STD-883, Class B DESCRIPTION: The IDT6178 is a high-speed cache address comparator sub-system consisting of a 16,384-bit StaticRAM organized as 4K x 4. Cycle Time and Address to MATCH Valid are equal. The IDT6178 features an onboard 4-bit comparator that compares RAM contents and current input data. The result is an active HIGH on the MATCH pin. The MATCH pins of several IDT6178s can be handed together to provide enabling or acknowledging signals to the data cache or processor. The IDT6178 is fabricated using IDT’s high-performance, high-reliability CMOS technology. Address to MATCH and Data to MATCH times are as fast as 10ns. All inputs and outputs of the IDT6178 are TTL-compatible and the device operates from a single 5V supply. The IDT6178 is packaged in either a 22-pin, 300-mil Plastic or Ceramic DIP package or 24-pin SOJ. Military grade product is manufactured in compliance with latest revision of MIL- STD-883, Class B, making it ideally suited to military tempera- ture applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM The IDT logo is a registered trademark of Integrated Device Technology, Inc. 1 A0 2953 drw 01 A11 ADDRESS DECODE I/O0 – I/O3 WE OE CLR CONTROL 16,384-BIT MEMORY ARRAY CONTROL I/O COMPARATOR CLEAR MEMORY ARRAY 4 4 4 4 MATCH VCC GND 11.1 |
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