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ICS9169F-01 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS9169F-01 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 10 page 6 ICS9169-01 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used at 50MHz and higher clock loads. 3) Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01µF ceramic Connections to VDD: |
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