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MK2049-36SI Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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MK2049-36SI Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 10 page MK2049-36 3.3 V Communications Clock PLL MDS 2049-36 A 3 Revision 120400 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com PRELIMINARY INFORMATION Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (Note 1) ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage, VDD Referenced to GND 7 V Inputs and Clock Outputs -0.5 VDD+0.5 V Ambient Operating Temperature -40 85 °C Soldering Temperature Max of 10 seconds 250 °C Storage Temperature -65 150 °C DC CHARACTERISTICS (VDD = 3.3 V unless noted) DC CHARACTERISTICS (VDD = 3.3 V unless noted) Operating Voltage, VDD 3.15 3.3 3.45 V Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Output High Voltage, VOH, CMOS level IOH=-4 mA VDD-0.4 V Output High Voltage, VOH IOH=-8 mA 2.4 V Output Low Voltage IOL=8 mA 0.4 V Operating Supply Current, IDD No Load, VDD=3.3 V 7 mA Short Circuit Current Each output ±50 mA Input Capacitance, FS3:0 5 pF AC CHARACTERISTICS (VDD = 3.3 V unless noted) AC CHARACTERISTICS (VDD = 3.3 V unless noted) Input Frequency, External Mode ICLK 8.000 kHz Input Clock Pulse Width 10 ns Propagation Delay ICLK to 8 kHz 7 ns Delay, CLK/2 after CLK 1 ns Output Clock Rise Time 0.8 to 2.0 V 2 ns Output Clock Fall Time 2.0 to 0.8 V 2 ns Output Clock Duty Cycle, High Time At VDD/2, except 8k 40 60 % Actual mean frequency error versus target Any clock selection 0 0 ppm Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. Electrical Specifications |
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