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ICS9248-78 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS9248-78 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 13 page 6 ICS9248- 78 Preliminary Product Preview Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable) t i B n o i t p i r c s e D D W P 7 t i B m u r t c e p S d a r e p S r e t n e C % 5 2 . 0 ± - 0 0 % 5 . 0 - o t 0 m u r t c e p S d a e r p S n w o D - 1 t i B ) 4 : 6 , 2 ( t i B ) 4 : 6 , 2 ( K L C U P C z H M M A R D S z H M K L C I C P z H M z H M 6 6 V 3 z H M C I P A O I 1 e t o N 0 = 6 6 V 3 _ L E S1 = 6 6 V 3 _ L E S 0 0 0 03 2 . 0 0 13 2 . 0 0 11 4 . 3 32 8 . 6 62 8 . 6 60 7 . 6 1 1 0 0 00 9 . 0 0 10 9 . 0 0 13 6 . 3 36 2 . 7 66 2 . 7 61 8 . 6 1 0 1 0 00 0 . 5 0 10 0 . 5 0 10 0 . 5 30 0 . 0 70 0 . 0 70 5 . 7 1 1 1 0 09 8 . 6 63 3 . 0 0 14 4 . 3 39 8 . 6 69 8 . 6 62 7 . 6 1 0 0 1 00 0 . 0 2 10 0 . 0 2 10 0 . 0 4* 0 0 . 4 60 0 . 0 80 0 . 0 2 1 0 1 00 0 . 4 2 10 0 . 4 2 13 3 . 1 4* 0 0 . 4 66 6 . 2 87 6 . 0 2 0 1 1 00 3 . 3 3 10 3 . 3 3 13 4 . 4 4* 0 0 . 4 66 8 . 8 81 2 . 2 2 1 1 1 00 3 . 3 3 10 3 . 3 3 12 3 . 3 35 6 . 6 65 6 . 6 66 6 . 6 1 0 0 0 10 0 . 0 4 10 0 . 0 4 10 0 . 5 30 0 . 0 70 0 . 0 70 5 . 7 1 1 0 0 10 0 . 0 5 10 0 . 0 5 10 5 . 7 3* 0 0 . 4 60 0 . 5 75 7 . 8 1 0 1 0 19 9 . 4 1 19 9 . 4 1 13 3 . 8 3* 0 0 . 4 66 6 . 6 76 1 . 9 1 1 1 0 10 0 . 0 70 0 . 5 0 10 0 . 5 30 0 . 0 70 0 . 0 70 5 . 7 1 0 0 1 10 0 . 5 70 5 . 2 1 10 5 . 7 3* 0 0 . 4 60 0 . 5 75 7 . 8 1 1 0 1 11 3 . 3 86 9 . 4 2 15 6 . 1 4* 0 0 . 4 61 3 . 3 83 8 . 0 2 0 1 1 10 0 . 0 90 0 . 0 90 0 . 0 30 0 . 0 60 0 . 0 60 0 . 5 1 1 1 1 10 0 . 5 90 0 . 5 97 6 . 1 33 3 . 3 63 3 . 3 63 8 . 5 1 3 t i B s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r F - 0 4 : 6 , 2 t i B y b d e t c e l e s s i y c n e u q e r F - 1 0 1 t i B l a m r o N - 0 e l b a n e m u r t c e p s d a e r p S - 1 1 0 t i B g n i n n u R - 0 s t u p t u o l l a e t a t s i r T - 1 0 Notes: 1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000. * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation. |
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