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ICS9248-50 Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS9248-50 Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 11 page 9 ICS9248-50 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user All unmarked capacitors are 0.01µF ceramic |
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