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ICS9248-39 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS9248-39 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 16 page 6 ICS9248-39 Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable) Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B- 1 ) d e v r e s e R ( 3 t i B- X # 1 S F d e h c t a L 2 t i B- 1 ) d e v r e s e R ( 1 t i B- X # 3 S F d e h c t a L 0 t i B- 1 ) d e v r e s e R ( t i B# n i PD W Pn o i t p i r c s e D 7 t i B- 1 ) d e v r e s e R ( 6 t i B- 1 ) d e v r e s e R ( 5 t i B- 1 ) d e v r e s e R ( 4 t i B7 41 ) t c a n I / t c A ( 0 C I P A O I 3 t i B- 1 ) d e v r e s e R ( 2 t i B- 1 ) d e v r e s e R ( 1 t i B6 41 ) t c a n I / t c A ( 1 F E R 0 t i B2 1 ) t c a n I / t c A ( 0 F E R |
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