7

ICS9148-12

Notes:

1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.

y

t

i

l

a

n

o

i

t

c

n

u

FU

P

C

,

I

C

P

F

_

I

C

P

M

A

R

D

SF

E

RC

I

P

A

O

I

z

H

M

4

2

n

o

i

t

c

e

l

e

S

z

H

M

8

4

n

o

i

t

c

e

l

e

S

e

t

a

t

s

i

r

TZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

H

e

d

o

m

t

s

e

T2

/

K

L

C

T

1

4

/

K

L

C

T

1

2

/

K

L

C

T

1

K

L

C

T

1

K

L

C

T

1

4

/

K

L

C

T

1

2

/

K

L

C

T

1

Select Functions

Serial Configuration Command Bitmaps

Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0)

(default on Bits 3, 2 = 1)

Note: PWD = Power-Up Default

T

I

B#

N

I

PN

O

I

T

P

I

R

C

S

E

DD

W

P

7

t

i

B-

d

e

v

r

e

s

e

R0

6

t

i

B-

n

o

i

t

a

r

e

p

o

l

a

m

r

o

n

r

o

f

0

e

b

t

s

u

M0

5

t

i

B-

e

p

y

t

s

l

o

r

t

n

o

C

,

m

u

r

t

c

e

p

S

d

a

e

r

p

S

n

I

)

d

a

e

r

p

s

n

w

o

d

=

1

,

d

e

r

e

t

n

e

c

=

0

(

0

4

t

i

B

g

n

i

d

a

e

r

p

S

s

l

o

r

t

n

o

C

,

m

u

r

t

c

e

p

S

d

a

e

r

p

S

n

I

)

%

6

.

0

=

1

%

8

.

1

=

0

(

0

3

t

i

B3

2z

H

M

4

2

=

0

,

z

H

M

8

4

=

1

)

t

c

e

l

e

S

y

c

n

e

u

q

e

r

F

(

z

H

M

4

2

/

8

41

2

t

i

B2

2z

H

M

4

2

=

0

,

z

H

M

8

4

=

1

)

t

c

e

l

e

S

y

c

n

e

u

q

e

r

F

(

z

H

M

4

2

/

8

41

1

t

i

B

0

t

i

B

-

1

t

i

B

1

1

0

0

0

t

i

B

e

t

a

t

S

-

i

r

T

-

1

e

l

b

a

n

E

m

u

r

t

c

e

p

S

d

a

e

r

p

S

-

0

e

d

o

m

t

s

e

T

-

1

n

o

i

t

a

r

e

p

o

l

a

m

r

o

N

-

0

0

0