2

ICS9148-11

Pin Descriptions

Power Groups

VDD1 = REF0, X1, X2

VDD2 = PCICLK_F, PCICLK (0:5)

VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#,

SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core.

VDDL1 = IOAPIC (0:1)

VDDL2 = CPUCLK (0:3)

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

2

REF0

OUT

14.318 MHz reference clock outputs.

3, 9, 16, 22, 27,

33, 39, 45

GND

PWR

Ground.

4X1

IN

XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed

back resistor from X2

5

X2

OUT

XTAL_OUT Crystal output, has internal load cap 33pF

25

MODE

IN

Mode select pin for enabling power management features.

7

PCLK_F

OUT

Free running BUS clock during PCI_STOP# = 0.

8, 10, 11, 12

13, 15

PCICLK (0:5)

OUT

BUS clock outputs.

26

OE

IN

Logic input for output enable, tristates all outputs when low.

23

SDATA

IN

Serial data in for serial config port.

24

SCLK

IN

Clock input for serial config port.

1, 6, 14,

19, 30, 36,

VDD1, VDD2,

VDD3

PWR

Nominal 3.3V power supply, see power groups for function.

17, 18, 20, 21,

32, 34, 35, 37, 38

SDRAM

(0:4) (8:11)

OUT

SDRAM clocks 66.6MHz.

42, 48

VDDL2, VDDL1

PWR

CPU and IOAPIC clock power supply, either

2.5 or 3.3V nominal

40, 41, 43, 44

CPUCLK (0:3)

OUT

CPU output clocks, powered by VDDL2 (66.6 MHz)

46, 47

IOAPIC (0:1)

OUT

IOAPIC clock output, (14.318 MHz) powered by VDDL1

28

SDRAM7

OUT

SDRAM clock 66.6 MHz selected

PCI_STOP#

IN

Halts PCICLK (0:5) at logic "0" level when low

29

SDRAM6

OUT

SDRAM clock 66.6 MHz selected

CPU_STOP#

IN

Halts CPUCLK clocks at logic "0" level when low

31

SDRAM5

OUT

SDRAM clock 66.6 MHz selected

PWR_DWN#

IN

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