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ICS8431CM-11 Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS8431CM-11
Description  255MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8431CM-11 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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ICS8431CM-11
www.icst.com/products/hiperclocks.html
REV. A JULY 11, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8431-11
255MHZ, LOW JITTER,
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8431-11 is a general purpose clock
frequency synthesizer for IA64/32 application and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The VCO
operates at a frequency range of 190MHz to
510MHz providing an output frequency range of 95MHz to
255MHz. The output frequency can be programmed using the
parallel interface, M0 thru M8, to the configuration logic.
Spread spectrum clocking is programmed via the control
inputs SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431-11 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-11 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
XTAL1
XTAL2
M0:M8
PLL
FOUT
nFOUT
÷ 16
TEST_I/O
OSC
VCO
÷ 2
PHASE
DETECTOR
÷ M
SSC
Control
Logic
Configuration
Logic
nP_LOAD
SSC_CTL0
FEATURES
• Fully integrated PLL
• Differential 3.3V LVPECL output
• Programmable PLL loop divider for generating a variety of
output frequencies.
• Crystal oscillator interface
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI
• Typical RMS cycle-to-cycle jitter 2.6 ps
• LVTTL / LVCMOS control inputs
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 3.3V supply voltage
• 28 lead SOIC
• 0°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
SSC_CTL1
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
MR
nc
VDDO
FOUT
nFOUT
VEE
ICS8431-11
28-Lead SOIC
M Package
Top View
HiPerClockS™
,&6


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