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ICS552-02 Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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ICS552-02 Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 6 page LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK MDS 552-02 B 5 Revision 050401 Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q w w w. icst . c om PRE L IMINA R Y INF O RMA T IO N ICS552-02 AC Electrical Characteristics VDD = 2.5V ±5%, Ambient Temperature 0 to +70 ° C, unless stated otherwise VDD = 3.3V ±5%, Ambient Temperature 0 to +70 ° C, unless stated otherwise VDD = 5.0V ±5%, Ambient Temperature 0 to +70 ° C, unless stated otherwise Notes: 1. With rail-to-rail input clock. 2. Between any two outputs with equal loading. 3. Propagation delay matching through the part. 4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock generators. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 1.5 ns Propagation Delay Note 1 3.5 ns Output to output skew Note 2 Rising edges at VDD/2 0 50 ps Input A to Input B skew Note 3 0 50 ps Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 1.0 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 1.0 ns Propagation Delay Note 1 3.0 ns Output to output skew Note 2 Rising edges at VDD/2 0 50 ps Input A to Input B skew Note 3 0 50 ps Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 0.7 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 0.7 ns Propagation Delay Note 1 2.8 ns Output to output skew Note 2 Rising edges at VDD/2 0 50 ps Input A to Input B skew Note 3 0 50 ps |
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