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ICS527R-01I Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS527R-01I Datasheet(HTML) 6 Page - Integrated Circuit Systems |
6 / 8 page ICS527-01 Clock Slicer™ User Configurable Zero Delay Buffer MDS 527-01 B 6 Revision 020801 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA•95126•(408)295-9800tel • www.icst.com Multiple Output Example In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the MK74CB217 which has dual 1 to 8 buffers with low pin to pin skew. 125 MHz 0.01 µF 0.01 µF 25 MHz R5 R6 DIV2 S0 S1 VDD ICLK FBIN GND GND R4 R3 R2 R1 R0 VDD CLK1 CLK2 OECLK2 2XDRIVE F0 F1 F2 F6 F5 F4 F3 PDTS INA QA0 QA1 QA2 VDD VDD QA3 QA4 GND GND INB VDD QB3 QA5 QA6 GND QA7 OEA QB5 QB6 QB7 OEB QB0 QB1 QB2 VDD QB4 GND 0.01 µF 0.01 µF VDD This configuration produces the following waveforms: 125 MHz, ICLK 25 MHz, QA0-7 50 MHz, QB0-7 Using the equation for selecting the dividers gives: 25 MHz = 125 MHz • (FDW + 2) (RDW + 2) If FDW = 0, then RDW = 8. This gives the required divide-by-5 function. Setting pin DIV2 = 1 gives both a 25 MHz and 50 MHz output from the ICS527-01. The FBIN pin is connected to the QA7 output of the MK74CB217. This aligns all the outputs of the MK74CB217 with the 125 MHz input since the ICS527-01 aligns rising edges on the ICLK and FBIN pins. In this example, series termination resistors have been omitted for clarity but should be used on all clock outputs. |
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