HY51V65163HG datasheet(8/11 Pages) HYNIX

Part #	HY51V65163HG

Description	4M x 16Bit EDO DRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

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HY51V(S)65163HG/HGL

Rev 0.1 / Apr. 01

Extended Data Out Mode Cycles

EDO Page Mode Read-Modify-Write Cycle

Self Refresh Cycle (L-Version)

Parameter

Symbol

-45

-50

-60

Unit

Note

Min

Max

Min

Max

Min

Max

EDO page mode cyle time

tHPC

17

-

20

-

25

-

ns

25

Write pulse width during /CAS precharge

tWPE

7

-

8

-

10

-

ns

EDO mode /RAS pulse width

tRASP

-

100K

-

100K

-

100K

ns

16

Access time from /CAS precharge

tACP

-

28

-

28

-

35

ns

9,17,22

/RAS hold time from /CAS precharge

tRHCP

26

-

28

-

35

-

ns

/CAS hold time referred /OE

tCOL

7

-

8

-

10

-

ns

/CAS to /OE set-up time

tCOP

5

-

5

-

5

-

ns

Read command hold time

from /CAS precharge

tRCHP

26

-

28

-

35

-

ns

Output data hold time from /CAS low

tDOH

3

-

3

-

3

-

ns

9,27

/OE precharge time

tOEP

7

-

8

-

10

-

ns

Parameter

Symbol

-45

-50

-60

Unit

Note

Min

Max

Min

Max

Min

Max

EDO read-modify-write cycle time

tHPRWC

57

-

57

-

68

-

ns

EDO page mode read-modify-write cycle

/CAS precharge to /WE delay time

tCPW

45

-

45

-

54

-

ns

14,22

Parameter

Symbol

-45

-50

-60

Unit

Note

Min

Max

Min

Max

Min

Max

/RAS pulse width ( self refresh)

tRASS

100

-

100

-

100

-

us

31

/RAS precharge time ( self refresh)

tRPS

90

-

90

-

110

-

ns

31

/CAS hold time ( self refresh)

tCHS

-50

-

-50

-

-50

-

ns

23

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