 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HMS97C8032 Datasheet(PDF) 11 Page - Hynix Semiconductor |
|
||||||||||||||||||||||||||||||
HMS97C8032 Datasheet(HTML) 11 Page - Hynix Semiconductor |
|
|
11 / 157 page  HMS91C8032/97C8032 8 NOV., 2001 Ver 1.02 HMS91C8032/HMS97C8032 Description 3. INSTRUCTION SET The HMS9XC8032 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for one-bit variables as a separate data type, allowing direct bit manipulation in control and logic systems that require Boolean processing. 3.1 Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW, shown in Figure 3-1, resides in the SFR space. It contains the Carry bit, the Aux- iliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a Parity bit, and two user-definable status flags. The Carry bit, other than serving the functions of a Carry bit in arithmetic operations, also serves as the “Accumulator” for a number of Boolean operations. RS0 and RS1 are used to select one of the four register banks. Each register bank composed of eight registers.(R0 to R7) The selection of a register bank is made at execution time. The parity bit reflects the number of 1s in the Accumulator: P= 1 if the Accumulator contains an odd number of 1s, and P = 0 if the Accumulator contains an even number of 1s. Thus the number of 1s in the Accumulator plus P is always even. Two bits in the PSW are uncommitted and may be used as general-purpose status flags. 3.2 Addressing Modes The addressing modes in the HMS9XC8032 instruction set are as follows: Direct Addressing In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs can be directly addressed. Indirect Addressing In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the se- lected bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit "data pointer" register, DPTR. Figure 3-1 PSW (Program Status Word) Register in HMS9XC8032 Devices AC - CY F0 RS0 OV P PSW 6 Auxiliary carry flag receives carry out from bit 3 of addition operands PSW 0 Parity of accumulator set by hardware to 1 if it contains an odd number of 1s; otherwise it is reset to 0 PSW 1 User-definable flag PSW 2 Overflow flag set by arithmetic operation PSW 3 Register bank select bit 0 PSW 7 Carry flag receives carry out from bit 7 of ALU operands PSW 4 Register bank select bit 1 PSW 5 General purpose status flag RS1 |
Similar Part No. - HMS97C8032 |
|
Similar Description - HMS97C8032 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
