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GM71V18163C-7 Datasheet(PDF) 5 Page - Hynix Semiconductor |
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GM71V18163C-7 Datasheet(HTML) 5 Page - Hynix Semiconductor |
5 / 11 page GM71VS18163CL GM71V18163C Rev 0.1 / Apr’01 Capacitance (VCC = 3.3V+/-0.3V, TA = 25C) Symbol Parameter Note CI1 CI2 CI/O Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out) 1 1 1, 2 Unit pF Max 5 7 7 Min - - - Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable DOUT. AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Note 1, 2, 18, 19, 20) Test Conditions Input rise and fall times : 2 ns Output timing reference levels : 0.8V, 2.0V Input levels : VIL = 0V, VIH = 3V Output load : 1TTL gate + CL (100 pF) Input timing reference levels : 0.8V, 2.0V (Including scope and jig) pF pF Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter Note Max Unit Min Max Min Max Min tRC Random Read or Write Cycle Time 84 - 104 - 124 - tRP RAS Precharge Time 30 - 40 - 50 - tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 tCAS CAS Pulse Width 8 10,000 10,000 10,000 10 13 tASR Row Address Set up Time 0 - - - 0 0 tRAH Row Address Hold Time 8 - - - 10 10 tASC Column Address Set-up Time 0 - - - 0 0 tCAH Column Address Hold Time 8 - - - 10 13 tRCD RAS to CAS Delay Time 12 37 45 52 14 14 3 tRAD RAS to Column Address Delay Time 10 25 30 35 12 12 4 tRSH RAS Hold Time 10 - - - 13 13 tCSH CAS Hold Time 35 - - - 40 45 tCRP CAS to RAS Precharge Time 5 - - - 5 5 tT Transition Time (Rise and Fall) 2 50 50 50 2 2 7 tDZO OE Delay Time from DIN 0 - - - 0 0 tDZC CAS Delay Time from DIN 0 - - - 0 0 GM71V(S)18163 C/CL-5 OE to DIN Delay Time 13 - - - 15 18 5 6 6 tCP CAS Precharge Time 8 - 10 - 13 - tODD GM71V(S)18163 C/CL-6 GM71V(S)18163 C/CL-7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 21 22 23 |
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