GM71CS18163CL

GM71C18163C

Rev 0.1 / Apr’01

15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to

WE leading edge in delayed write or read-modify-write cycles.

18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

19. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the

device. LCAS and UCAS cannot be staggered within the same write/read cycles.

20. All the Vcc and Vss pins shall be supplied with the same voltages.

or LCAS.

write cycles. It both write and read operation are mixed in a EDO mode RAS cycle(EDO

in EDO mode mix cycle (1) and (2).

When output buffers are enabled once,

sustain the low impedance state until valid data

is obtained.

When output buffer is turned on and off within a very short time , generally

Data output turns off and becomes high impedance from later rising edge of RAS and CAS.

Hold time and turn off time are specified by the timing specification of later rising edge of

EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high

during CAS high, the data will not come out until next CAS access. When WE goes low

during CAS high, the data will not come out until next CAS access.

RAS

25.

26.

29.

27.

28.

30.