Atmel AT697E [ERRATA SHEET]

4409D-AERO-04/12

3

4.

Wrong PC stored during FPU exception trap

When a trap is taken by the processor, the program counter (PC) is stored into %l1 of the trap window and the next

program counter (nPC) is stored into %l2. This operation works correctly for all traps except FPU exception (trap type

0x08). During FPU exception, the nPC is erroneously stored into both %l1 and %l2. This means that the exception

handler can not return and re-execute the trapped FPU instruction. During normal operation, this is not a problem since

re-executing the trapped instruction would just cause the instruction to trap again.

Workarounds

Return from FPU exception by restoring the execution address from %l2 (nPC) only, thus skipping the trapped FPU

instruction (this is usually performed by a JMPL %l2, %g0 / RETT %l2 + 4 instruction sequence).

5.

Single-stepping over SWAP and LDSTUB instruction locks AHB bus

During a debug session using the debug support unit (DSU), it is possible to perform singlestepping. If an attempt to

single-step a SWAP or LDSTUB instruction is made, the AHB bus will be locked and further debugging will be

impossible. The reason for this behaviour is that SWAP and LDSTUB instruction perform a read-modify-write cycle

which locks the AHB bus to insure atomicity. When such an instruction is single-stepped, the lock signal will be kept

active even after the processor enters debug mode, thereby preventing further bus arbitration. Since the

communications with the DSU is done over the AHB bus, further debugging is impossible and the device is in principle

dead-locked. This state can only be exited by deasserting the DSUEN signal (resuming execution) or asserting the

RESET signal.

Workarounds

Do not single-step over SWAP and LDSTUB instructions. Instead, set a breakpoint on the instruction right after the

SWAP/LDSTUB instruction and resume normal execution.

6.

Divide overflow will not clear zero flag

The divide instructions SDIVCC and UDIVCC set the integer condition codes (negative, overflow and zero) with respect

to the final result. When a divide overflow occurs, a pre-defined non-zero value is returned, the overflow bit is set and

the zero bit is cleared. However, under certain overflow conditions, the zero bit is wrongly set even though the result is

always nonzero.

Workarounds

If direct control over assembly language is possible, simply do not rely on the zero bit flag on a divide overflow. If direct

control over assembly language is not possible (high-level programming language such as C), activate the appropriate

compiler options to prevent the compiler from using the divide instructions (if using LECCS / BCC / RCC compilers, do

not use the -mv8 compiler flag).

7.

Register file fault-injection incorrectly implemented

Caution:

AT697E configuration of

the model.

8.

‘Data cache tag’ Error Counter Counting Error

The data tag error counter doesn’t show the correct number of errors.

If a data tag error is detected on a write cycle, the data cache is not updated but the tag error is counted. Since the tag

is not written the error remains, and on sub-sequent writes to the same address the error will be counted again.

It is also possible that a tag error occurs on the same address offset as an on-chip register. A tag error will then be

reported every time the register is accessed, since the access is not cacheable and the tag will not be written. If the

application software does not use this particular location of the cache, the error will never be removed but continously

reported.