GDC21D301A datasheet(8/35 Pages) HYNIX

Part #	GDC21D301A

Description	Transport Decoder

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Manufacturer	HYNIX [Hynix Semiconductor]

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GDC21D301A

Pin Description (continued)

NAME

TYPE

DESCRIPTION

HOST PROCESSOR INTERFACE

\DSP_STRB

127

I

Host Strobe (active low) : Asynchronous.

Used by the host processor to access the GDC21D301A. When

DSP_STRB

signal

is

active,

DSP_ADDR[22:0],

DSP_DATA[15:0], and DSP_PD should be valid.

DSP_RWB

128

I

Read/Write (active low) : Asynchronous.

The state of this signal defines data transfer type.

0 : Write to the device

1: Read from the device

\DSP_PD

129

I

Transport Decoder Chip Selection (active low).

This signal is used to activate and access the internal registers

of the GDC21D301A, the video decoder, the audio decoder, the

data decoder, and DRAM.

DSP_ADDR[22:0]

133,134,135,

136,137,138,

139,140,141,

142,143,144,

145,146,147,

148,149,150,

151,152,153,

154,155

I

Host Address Bus.

These signals are connected to the address bus of the host

processor interfaced with the GDC21D301A, the video

decoder, the audio decoder, the data decoder, and DRAM.

0x4FFFFF ~ 0x4C0000 : Transport Decoder address space

0x5BFFFF ~ 0x480000 : Video decoder space

0x47FFFF ~ 0x440000 : Audio decoder space

0x43FFFF ~ 0x400000 : Auxiliary data decoder space

0x3FFFFF ~ 0x000000 : DRAM space

BIT8MODE

156

I

Host Interface Mode Selection.

0 : 16-bit data bus interface

1 : 8-bit data bus interface

DSP_DATA[15:0]

3, 2, 1, 176,

174,173,172,

171,169,168,

167,166,164,

163,162,161

I/O/Z

Host Data Bus.

These signals are connected to the address bus of external host

processor.

DSP_READY

6

O/Z

Data Acknowledge (active high)

DSP_INT

5

O

Interrupt Request (active high)

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