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MH1RT Datasheet(PDF) 2 Page - ATMEL Corporation |
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MH1RT Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 19 page 2 4110L–AERO–11/10 MH1RT Notes: 1. Nominal 2 Input NAND Gate FO = 2 at 3.3V. Design Design Systems Supported Atmel supports several major software systems for design with complete macro cell libraries, as well as utilities for checking the netlist and estimated pre-route delay simulations. The following design systems are supported: Table 1. List of Available MH1RT Matrices Device Number Typical Routable Gates Max Pad Count Max I/O Count Gate Speed(1) Max. Sites Count MH1099E 519,000 332 324 180 ps 920,385 MH1156E 764,000 412 404 180 ps 1,447,975 MH1242E 1,198,000 512 504 180 ps 2,275,377 MH1332E 1,634,000 596 588 180 ps 3,098,804 Table 2. Supported design systems System Available Tools Cadence NCsim® - Verilog Simulator Encounter™ - Floorplanner RTL compiler® - Synthesis (Ambit) Mentor/Model Tech Questasim/Modelsim Verilog and VHDL (VITAL) Simulator DFT - Scan insertion and ATPG, BIST Synopsys® Design Compiler™ - Synthesis Primetime® - Static Path Formality® - Equivalence Checking DFTmax - Scan insertion and ATPG |
Similar Part No. - MH1RT_14 |
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Similar Description - MH1RT_14 |
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