UR5596

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

7 of 12

www.unisonic.com.tw

QW-R502-045,C

TYPICAL APPLICATION CIRCUITS

Following demonstrate several different application circuits to illustrate some of the options that are possible in

configuring the UTC UR5596. The individual circuit performance can be found in the Typical Performance

STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME

SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination

scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered

with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one

Figure 1. SSTL-Termination Scheme

FOR SSTL-2 APPLICATIONS

For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all

the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and

component count and selection.

+

+

+

GND

SHDN

SHDN

UTC UR5596

Figure 2. Recommended SSTL-2 Implementation