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UR5596-S08-T Datasheet(PDF) 8 Page - E-Tech Electronics LTD |
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UR5596-S08-T Datasheet(HTML) 8 Page - E-Tech Electronics LTD |
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8 / 12 page  UR5596 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 8 of 12 www.unisonic.com.tw QW-R502-045,C TYPICAL APPLICATION CIRCUITS(Cont.) Figure 3 illustrate another application that the power rails are split when power dissipation or efficiency are concerned. The output stage (PVIN) can be as lower as 1.8V, and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current from VTT, but the disadvantage of this circuit is the maximum continuous current is reduced. + + + VTT VDDQ VSENSE VREF GND SHDN AVIN PVIN CIN SHDN VDDQ=2.5V AVIN=2.2V ~ 5.5V COUT CREF VREF=1.25V VTT=1.25V UTC UR5596 PVIN=1.8V Figure 3. Lower Power Dissipation SSTL-2 Implementation The third optional application is that PVIN connect to 3.3V and AVIN will be always limited to operation on the 3.3V or 5V to always equal or higher than PVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. The power dissipation increasing problem must be careful to prevent the junction temperature to exceed the maximum ranting. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V rail. + + + VTT VDDQ VSENSE VREF GND SHDN AVIN PVIN CIN SHDN VDDQ=2.5V AVIN=3.3V or 5.5V COUT CREF VREF=1.25V VTT=1.25V UTC UR5596 PVIN=3.3V Figure 4. SSTL-2 Implementation with higher voltage rails |
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