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AT89LP6440 Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT89LP6440 Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 200 page  9 3706C–MICRO–2/11 AT89LP3240/6440 2.3 Comparison to Standard 8051 The AT89LP3240/6440 is part of a family of devices with enhanced features that are fully binary compatible with the 8051 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89C2051. The major differences from the standard 8051 are outlined in the following paragraphs and may be useful to users migrating to the AT89LP3240/6440 from older devices. 2.3.1 System Clock The maximum CPU clock frequency equals the externally supplied XTAL1 frequency. The oscil- lator is not divided by 2 to provide the internal clock and X2 mode is not supported. The System Clock Divider can scale the CPU clock versus the oscillator source (See Section 6.5 on page 32). 2.3.2 Reset The RST pin of the AT89LP3240/6440 is active-LOW as compared with the active-high reset in the standard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles, to be recognized as a valid reset. 2.3.3 Instruction Execution with Single-cycle Fetch The CPU fetches one code byte from memory every clock cycle instead of every six clock cycles. This greatly increases the throughput of the CPU. As a consequence, the CPU no longer executes instructions in 12, 24 or 48 clock cycles. Each standard instruction executes in only 1 to 4 clock cycles. See “Instruction Set Summary” on page 143 for more details. Any software delay loops or instruction-based timing operations may need to be retuned to achieve the desired results. 2.3.4 Interrupt Handling The interrupt controller polls the interrupt flags during the last clock cycle of any instruction. In order for an interrupt to be serviced at the end of an instruction, its flag needs to have been latched as active during the next to last clock cycle of the instruction, or in the last clock cycle of the previous instruction if the current instruction executes in only a single clock cycle. The external interrupt pins, INT0 and INT1, are sampled at every clock cycle instead of once every 12 clock cycles. Coupled with the shorter instruction timing and faster interrupt response, this leads to a higher maximum rate of incidence for the external interrupts. The Serial Peripheral Interface (SPI) has a dedicated interrupt vector. The SPI no longer shares its interrupt with the Serial Port and the ESPI (IE2.2) bit replaces SPIE (SPCR.7). 2.3.5 Timer/Counters By default Timer0, Timer 1 and Timer 2 are incremented at a rate of once per clock cycle. This compares to once every 12 clocks in the standard 8051. A common prescaler is available to divide the time base for all timers and reduce the increment rate. The TPS 3-0 bits in the CLKREG SFR control the prescaler (Table 6-2 on page 33). Setting TPS 3-0 = 1011B will cause the timers to count once every 12 clocks. The external Timer/Counter pins, T0, T1, T2 and T2EX, are sampled at every clock cycle instead of once every 12 clock cycles. This increases the maximum rate at which the Counter modules may function. |
Similar Part No. - AT89LP6440_14 |
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Similar Description - AT89LP6440_14 |
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