9

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the serial output

(SO) pin requires the following sequence. After the CS line is pulled low to select a device, the

READ op-code is transmitted via the SI line followed by the byte address to be read (A15–A0;

see Table 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at

the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS

line should be driven high after the data comes out. The read sequence can be continued

since the byte address is automatically incremented and data will continue to be shifted out.

When the highest address is reached, the address counter will roll over to the lowest address,

allowing the entire memory to be read in one continuous read cycle.

WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two sep-

arate instructions must be executed. First, the device

instruction. Then a write (WRITE) instruction may be executed. Also, the address of the mem-

ory location(s) to be programmed must be outside the protected address field location

selected by the block write protection level. During an internal write cycle, all commands will

be ignored except the RDSR instruction.

A write instruction requires the following sequence. After the CS line is pulled low to select the

device, the WRITE op-code is trans‘mitted via the SI line followed by the byte address (A15–

A0) and the data (D7–D0) to be programmed (see Table 10). Programming will start after the

CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK

low-time immediately after clocking in the D0 (LSB) data bit.

The READY/BUSY status of the device can be determined by initiating a read status register

(RDSR) instruction. If Bit 0 = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle

has ended. Only the RDSR instruction is enabled during the write programming cycle.

The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte

of data is received, the five low-order address bits are internally incremented by one; the high-

order bits of the address will remain constant. If more than 32 bytes of data are transmitted,

the address counter will roll over and the previously written data will be overwritten. The

AT25080A/160A/320A/640A is automatically returned to the write disable state at the comple-

tion of a write cycle.

NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction

and will return to the standby state when CS is brought high. A new CS falling edge is required

to reinitiate the serial communication.

Table 10. Address Key

Address

AT25080A

AT25160A

AT25320A

AT25640A

Don’t

Care Bits