8

5087E–SEEPR–7/09

AT25010A/020A/040A/080A

A write instruction requires the following sequence. After the CS line is pulled low to select the

device, the WRITE op-code (including A8) is transmitted via the SI line followed by the byte

address (A7

A0) and the data (D7–D0) to be programmed. Programming will start after the CS

pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time

immediately after clocking in the D0 (LSB) data bit.

The READY/BUSY status of the device can be determined by initiating a read status register

(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle

has ended. Only the RDSR instruction is enabled during the write programming cycle.

The AT25010A/020A/040A is capable of an 8-byte page write operation. After each byte of data

is received, the three low-order address bits are internally incremented by one; the six high-

order bits of the address will remain constant. If more than eight bytes of data are transmitted,

the address counter will roll over and the previously written data will be overwritten. The

AT25010A/020A/040A is automatically returned to the write disable state at the completion of a

write cycle.

NOTE: If the WP pin is brought low or if the device is not write enabled (WREN), the device will

ignore the Write instruction and will return to the standby state when CS is brought high. A new

CS falling edge is required to reinitiate the serial communication.

6.

Timing Diagrams

Figure 6-1.

Synchronous Data Timing (for Mode 0)

SO

V

OH

V

OL

HI-Z

HI-Z

t

V

VALID IN

SI

V

IH

V

IL

t

H

t

SU

t

DIS

SCK

V

IH

V

IL

t

WH

t

CSH

CS

V

IH

V

IL

t

CSS

t

CS

t

WL

t

HO