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ATTINY15L Datasheet(PDF) 9 Page - ATMEL Corporation |
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ATTINY15L Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 85 page 9 ATtiny15L 1187H–AVR–09/07 Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), and LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). Subroutine and Interrupt Hardware Stack The ATtiny15L uses a 3-level-deep Hardware Stack for subroutines and interrupts. The Hardware Stack is nine bits wide and stores the Program Counter (PC) return address while subroutines and interrupts are executed. RCALL instructions and interrupts push the PC return address onto Stack level 0, and the data in the other Stack levels 1 - 2 are pushed one level deeper in the Stack. When a RET or RETI instruction is executed the returning PC is fetched from Stack level 0, and the data in the other Stack levels 1 - 2 are popped one level in the Stack. If more than three subsequent subroutine calls or interrupts are executed, the first val- ues written to the Stack are overwritten. Pushing four return addresses A1, A2, A3, and A4 followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once more A2 from the Hardware Stack. The EEPROM Data Memory The ATtiny15L contains 64 bytes of data EEPROM memory. It is organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 36, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register. Memory Access and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 10 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 10. The Parallel Instruction Fetches and Instruction Executions Figure 11 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 |
Similar Part No. - ATTINY15L_14 |
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Similar Description - ATTINY15L_14 |
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