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AT90S4433 Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT90S4433 Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 126 page  8 AT90S/LS4433 1042H–AVR–04/03 The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, A/D Converters and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F. The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Programmable Flash memory. With the relative jump and call instructions, the whole 2K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM and, consequently, the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 8-bit Stack Pointer (SP) is read/write accessible in the I/O space. The 128 bytes of data SRAM can be easily accessed through the five different address- ing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. |
Similar Part No. - AT90S4433_14 |
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Similar Description - AT90S4433_14 |
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