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AT27C040 Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT27C040 Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 13 page 2 Atmel AT27C040 [DATASHEET] 0189J–EPROM–10/2012 2. Pin Configurations and Pinouts 3. Switching Considerations Switching between active and standby conditions via the Chip Enable (CE) pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance. At a minimum, a 0.1μF, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and ground terminals of the device — as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7μF bulk electrolytic capacitor should be utilized, again connected between the VCC and ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. Block Diagram Pin Name Function VPP Peak to Peak Voltage A0 - A18 Address Inputs O0 - O7 Outputs GND Ground CE Chip Enable OE Output Enable VCC Device Power Supply 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A7 A6 A5 A4 A3 A2 A1 A0 O0 A14 A13 A8 A9 A11 OE A10 CE O7 32-lead PLCC Top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 32-lead PDIP Top view VCC GND VPP A0 – A18 Address Inputs OE CE OE, CE, and Program Logic Y Decoder X Decoder Data Outputs O0 – O7 Output Buffers Y-Gating Cell Matrix Identification |
Similar Part No. - AT27C040_14 |
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Similar Description - AT27C040_14 |
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