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NB3N15552MNG Datasheet(PDF) 1 Page - ON Semiconductor |
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NB3N15552MNG Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2012 April, 2012 − Rev. 0 1 Publication Order Number: NB3N15552MN/D NB3Nxxxxx - VCXO Series 3.3V PureEdge ] VCXO Clock Generator with Differential LVPECL Outputs Description The NB3NXXXXX − series voltage−controlled crystal oscillator (VCXO) devices are designed to meet today’s requirements for 3.3 V LVPECL clock generation applications. These devices use an external high Q fundamental mode pullable crystal and Phase Locked Loop (PLL) multiplier to provide a wide range of frequencies from 60 MHz to 700 MHz (factory configurable per user specifications) with a pullable range of ±100 ppm. The silicon−based PureEdge products provides users with exceptional frequency stability and reliability. They produce an ultra low jitter and phase noise LVPECL differential out put . The NB3NXXXXX − series are members of ON Semiconductor’s PureEdge clock family that provides accurate and precision clock generation solutions. Available in the industry standard 4 mm x 4 mm QFN−20 package. Features • LVPECL Differential Output • Operating Range: 3.3 V ±10% • Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz) • 245 ps Typical Rise and Fall Times • Factory Configurable Frequencies from 60 MHz to 700 MHz (see Standard Frequencies in the Ordering Information Table in page 5) • Pullable Range Minimum of ±100 ppm • Control Voltage with Positive Slope • −40°C to +85°C Ambient Operating Temperature • These Devices are Pb−Free and are RoHS Compliant Applications • Networking • SONET • 10 Gigabit Ethernet • Networking Base Stations • Broadcasting MARKING DIAGRAM *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION http://onsemi.com (*Note: Microdot may be in either location) QFN20 MN SUFFIX CASE 485E XXXXX = Frequency XXX.XX A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb−Free Package NB3N xxxxx ALYWG G 1 20 Figure 1. Simplified Block Diagram of NB3Nxxxxx VDD CLK CLK GND OE VC XIN XOUT PLL Clock Multiplier |
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