ATA8402 [DATASHEET]

4982D–INDCO–07/14

6

4.3

CLK Output

An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load

capacitance is lower than 10pF.

4.3.1

Clock Pulse Take-over

it starts with an integrated RC-oscillator to switch on the ATA8402 with ENABLE = H, and after 1 ms assumes the clock

signal of the transmission IC, so that the message can be sent with crystal accuracy.

4.3.2

Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load

The delivered current pulse of the power amplifier is 9mA. The maximum output power is delivered to a resistive load of

465

Ω if the 1.0pF output capacitance of the power amplifier is compensated by the load impedance.

An optimum load impedance of:

The load impedance is defined as the impedance seen from the ATA8402’s ANT1, ANT2 into the matching network. Do not

confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF

amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 465

Ω where the parallel imaginary part should be kept

constant.

Output power measurement can be done with the circuit shown in Figure 4-2 on page 6. Note that the component values

must be changed to compensate for individual board parasitics until the ATA8402 has the right load impedance

Figure 4-2. Output Power Measurement

4.4

Application Circuit

st

placed as close as possible to the pins ANT1 and ANT2.

The loop antenna should not exceed a width of 1.5mm, otherwise the Q-factor of the loop antenna is too high.

the crystal. Normally, a 15pF load-capacitance crystal results in a value of 12pF.

1nF

2.2pF

33nH

ANT2

ANT1

Power

meter

50Ω

Z = 50Ω