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HI-8788PQT Datasheet(PDF) 2 Page - Holt Integrated Circuits

Part # HI-8788PQT
Description  ARINC INTERFACE DEVICE 16-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT
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Manufacturer  HOLTIC [Holt Integrated Circuits]
Direct Link  http://www.holtic.com
Logo HOLTIC - Holt Integrated Circuits

HI-8788PQT Datasheet(HTML) 2 Page - Holt Integrated Circuits

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HI-8787, HI-8788
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
PIN
SYMBOL
FUNCTION
DESCRIPTION
28
561 SYNC
digital output
ARINC 561 Sync signal
1, 3-10,13-15, 29-32
Dn
digital inputs
Parallel 16 bit bus input
11
GND
power supply
Ground
12
A0
digital input
Load address, A0=0 for 1st data load, A0=1 for 2nd data load
16
SLP1.5
digital input
Selects the slope of the line driver. High=1.5us
17
digital input
Write strobe. Loads data on rising edge.
18
digital input
Registers and sequencing logic initialized when low
19
XMIT CLK
digital input
Clock input for the transmitter
20
XMT RDY
digital output
Goes high if the buffer register is empty
21
PARITY ENB
digital input
When high the 32nd bit output is odd parity
22
V-
power supply
-10 volt rail
23
TXAOUT
analog output
Line driver output-A side
24
TXBOUT
analog output
Line driver output-B side
25
561 DATA
digital output
Serial output for ARINC 561 data
26
V+
power supply
+10 volt rail
27
VCC
power supply
+5 volt rail, “one” level out of line driver, inverted for “zero”
WRITE
RESET
The HI-8787 isa parallel to serial converter, which when
loaded with two 16 bit parallel words, outputs the data as a
32 bit serial word. Timing circuitry insertsa4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word
is being transmitted.
If the PARITY ENB pin is high, the 32nd bit will bea parity
bit, inserted so as to make the 32 bit word have odd parity. If
the PARITY ENB pin is low, the 32nd bit will be the D15 bit
of the 2nd word loaded.
Outputs are provided for both ARINC 429 (TXAOUT and
TXBOUT pins), and ARINC 561 (561 DATA and 561 SYNC
pins) type data.
A low signal applied to the
pin resets the HI-8787’s
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
The XMIT CLK frequency is the same as the data rate.
RESET
Input data can be loaded when the XMT RDY signal is
high, which indicates the input buffer register is empty. The
first 16 bit word is loaded with the A0 input high. The sec-
ond word is loaded with A0 in the low state. Each data word
is loaded into the input buffer register bya low pulse on the
input. (See figure 1). After the second word has
been loaded, the XMT RDY output goes low. The contents
of the input buffer register are transferred to the output reg-
ister during the fourth bit period of the gap. If the fourth gap
bit period of the previous word has already been transmit-
ted, the contents of the input buffer register will be trans-
ferred to the output shift register during the first bit period af-
ter the second data load, and the XMT RDY output goes
high.
After the output shift register is loaded, the data is shifted
out to the output logic in the order shown in figure 2.
WRITE
The 561 SYNC output pulses low when the XMIT CLK is
low during the 8th bit of the ARINC transmission.
HOLT INTEGRATED CIRCUITS
2
HOLT INTEGRATED CIRCUITS
2


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