The Decoder requiresa single clock witha frequency of 12

times the desired data rate applied at the DECODER

CLOCK input. The Manchester II coded data can be

presented to the Decoder in one of two ways. The

BIPOLAR ONE and BIPOLAR ZERO inputs will accept

data froma comparator sensed transformer coupled bus as

specified in MIL-STD-1553. The UNIPOLAR DATA input

can only accept non-inverted Manchester II coded data

(e.g. from

of an Encoder). The

Decoder is free running and continuously monitors its data

input lines fora valid sync character and two valid

Manchester data bits to start an output cycle. Whena valid

sync is recognized (1), the type of sync is indicated on

COMMAND/

SYNC output. If the sync character was

a command sync, this output will go high (2) and remain

high for sixteen DECODER SHIFT CLOCK periods (3),

otherwise it will remain low. The TAKE DATA output will go

high and remain high (2)- (3) while the Decoder is

transmitting the decoded data through SERIAL DATA OUT.

The decoded data available at SERIAL DATA OUT is ina

NRZ format. The DECODER SHIFT CLOCK is provided so

that the decoded bits can be shifted into an external register

on every low-to-high transition of this clock(2)- (3). After all

sixteen decoded bits have been transmitted (3) the data is

checked for odd parity.A high on VALID WORD output (4)

indicatesa successful reception ofa word without any

Manchester or parity errors. At this time the Decoder is

BIPOLAR ZERO OUT

DATA

HI-15530

HOLT INTEGRATED CIRCUITS

4

DECODER OPERATION

0

1

2

3

4

5

6

7

16

17

18

19

15

14

13

12

11

2

1

0

P

2

1

0

P

15

14

13

12

11

SYNC

SYNC

SYNC

15

14

13

12

3

2

1

0

SYNC

(1)(2)

(3)

(4)

May be high from previous reception

VALID WORD

DECODER

SHIFT CLK

TIMING

TAKE DATA

SERIAL

DATA OUT

BIPOLAR

ONE IN

BIPLOAR

ZERO IN

8

COMMAND/

SYNC

DATA

10

10

4

UNDEFINED

TAKE DATA

UNIPOLAR

DATA IN

BIPOLAR

ONE IN

BIPOLAR

ZERO IN

MASTER

RESET

DECODER

CLK

DECODER

RESET

COMMAND/

SYNC

DATA

SERIAL DATA

OUT

VALID

WORD

DECODER

SHIFT CLK

TRANSITION

FINDER

CHARACTER

IDENTIFIER

SYNCHRONIZER

BIT

COUNTER

BIT

RATE

CLK

PARITY

CHECK

looking fora new sync character to start another output

sequence. VALID WORD will go low approximately 20

DECODER SHIFT CLOCK periods after it goes high if not

reset low sooner bya valid sync and two valid Manchester

bits as shown (1). At any time in the above sequence,a

high input on DECODER RESET duringa low-to-high

transition of DECODER SHIFT CLOCK will abort

transmission and initialize the Decoder to start looking fora

new sync character.