FUNCTIONAL DESCRIPTION

Whenevera Logic "0" is applied to the Chip Select (

)

input, one bit of data is clocked into the shift register from the

serial data input (DIN) with each negative transition of the

Clock (

) input.

is internally tied to VSS on some

versions. A Logic "1" present at the Load (LD) input will

causea parallel transfer of data from the shift register to the

data latch. If the Load (LD) input is held high while data is

clocked into the shift register, the latch will be transparent.

To display segments,a Logic "1" is stored in the appropriate

shift register bit position, and the segment output is out-of-

phase with the backplane.

The backplane output functions in1 of2 modes; externally

driven or self-oscillating. When the LCDØ input is externally

driven with the LCDØOPT input open circuit (Figure 2), the

backplane output will be in-phase with LCDØ. Utilizing the

self-oscillating mode, inputs LCDØ and LCDØOPT are tied

together and connected to an RC circuit (Figure 3).

A 150K

resistor witha 470pF capacitor generates an

approximate backplane frequency of 100Hz. The

LCDØ/LCDØOPT oscillator frequency is divided by 256 to

determine the backplane output frequency.

The resistor

value (R) must be at least 30K

for proper self-oscillator

operation.

For displays havinga number of segments greater than 38,

two or more of the display drivers may be cascaded together

by connecting the serial data output (DOUT) from the first

driver, to the serial data input (DIN) of the following driver,

etc. (See Figures2& 3). Data out (DOUT) will change state

CS

CL

CS

W

All four logic inputs are TTL compatible on the HI-8010 and

CMOS compatible on the HI-8110.

W

HI-8010/HI-8110 Series

TIMING DIAGRAM

t

CSH

t

CSS

t

DS

t

DH

t

CL

t

CDO

t

LS

t

LW

t

CSL

t

LCS

CL

INPUT

DIN

INPUT

CS

INPUT

LD

INPUT

DOUT

OUTPUT

VALID

VALID

INTERNAL OSCILLATOR CIRCUIT

TO BACKPLANE

TRANSLATOR

AND DRIVER

÷ 256

LCDØ

OPT

LCDØ

Figure 1

Q

on the rising edge of the Clock (

). Clock (

), Load (LD)

and Chip Select (

) should be tied in common with each

other, respectively, between all cascaded display drivers.

CL

CL

CS

HOLT INTEGRATED CIRCUITS

3-4