HN58X24128I/HN58X24256I

8

Device Address (A0, A1, A2)

Eight devices can be wired for one common data bus line as maximum. Device address pins are used to

distinguish each device and device address pins should be connected to V

When device address

code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one

device can be activated.

Pin Connections for A0 to A2

Pin connection

Memory size

Max connect

number

A2

A1

A0

Note

128k bit

8

V

V

256k bit

8

V

V

V

Note:

1. “V

Write Protect (WP)

When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in

the following table. When the WP is low, write operation for all memory arrays are allowed. The read

operation is always activated irrespective of the WP pin status. WP should be fixed high or low during

operations since WP does not provide a latch function.

Write Protect Area

Write protect area

WP pin status 128k bit

256k bit

V

IH

Upper 1/8 (16k bit)

Upper 1/8 (32k bit)

V

IL

Normal read/write operation