HM658512A Series

7

At the end of self refresh, refresh reset time (t

the RAM. During t

If auto refresh follows self refresh, low

transition of

OE/RFSH at the beginning of automatic refresh must not occur during t

Notes on Using the HM658512A

Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive

than conventional SRAM’s.

(1) If a short

CE pulse of a width less than t

stored data may be destroyed. Make sure that

CE low pulses of less than t

that a 10 ns

CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is

generated by the decoding of higher address signals on the board. Avoid these short pulses.

(2)

OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an

incomplete refresh that will destroy data. Make sure that

OE/RFSH low pulse of less than t

also inhibited.

(3) t

function. The t

(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100

µs after the power voltage reaches 4.5 V-5.5 V after power-on.

Function Table

CE

OE/RFSH

WE

I/O pin

Mode

L

L

H

Dout

Read

L

X

L

High-Z

Write

L

H

H

High-Z

—

H

L

X

High-Z

Refresh

H

H

X

High-Z

Standby

Note:

X means H or L.