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HM658512A Datasheet(PDF) 7 Page - Hitachi Semiconductor |
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HM658512A Datasheet(HTML) 7 Page - Hitachi Semiconductor |
7 / 22 page HM658512A Series 7 At the end of self refresh, refresh reset time (t RFS) is required to reset the internal self refresh operation of the RAM. During t RFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not occur during t RFS period. Notes on Using the HM658512A Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive than conventional SRAM’s. (1) If a short CE pulse of a width less than t CE min is applied to RAM, an incomplete read occurs and stored data may be destroyed. Make sure that CE low pulses of less than t CE min are inhibited. Note that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is generated by the decoding of higher address signals on the board. Avoid these short pulses. (2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than t FAP min are also inhibited. (3) t OHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH function. The t OHC and tOCD specs must be strictly maintained. (4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100 µs after the power voltage reaches 4.5 V-5.5 V after power-on. Function Table CE OE/RFSH WE I/O pin Mode L L H Dout Read L X L High-Z Write L H H High-Z — H L X High-Z Refresh H H X High-Z Standby Note: X means H or L. |
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