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HM62V8512CI Datasheet(PDF) 11 Page - Hitachi Semiconductor |
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HM62V8512CI Datasheet(HTML) 11 Page - Hitachi Semiconductor |
11 / 13 page HM62V8512CI Series 11 Low V CC Data Retention Characteristics (Ta = –40 to +85°C) Parameter Symbol Min Typ Max Unit Test conditions* 2 V CC for data retention V DR 2— —V CS ≥ V CC – 0.2 V, Vin ≥ 0 V Data retention current I CCDR — 0.8* 3 20* 1 µA V CC = 3.0 V, Vin ≥ 0 V CS ≥ V CC – 0.2 V Chip deselect to data retention time t CDR 0 — — ns See retention waveform Operation recovery time t R t RC* 4 —— ns Notes: 1. For L-version and 10 µA (max.) at Ta = –40 to +40°C. 2. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state. 3. Typical values are at V CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 4. t RC = read cycle time. Low V CC Data Retention Timing Waveform (CS Controlled) V CC 2.7 V 2.4 V 0 V CS t CDR t R CS ≥ V CC – 0.2 V V DR Data retention mode |
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