6

HV9120

Supertex inc.

www.supertex.com

Doc.# DSFP-HV9120

B060412

required. In general, because the reference voltage of the

Supertex HV9120 is not noisy, as some previous examples

have been, overriding the reference should seldom be nec-

essary.

Because the reference of the HV9120 is a high impedance

node, and usually there will be significant electrical noise

near it, a bypass capacitor between the reference pin and

VSS is strongly recommended. The reference buffer ampli-

fier is intentionally compensated to be stable with a capaci-

tive load of 0.01 to 0.1µF.

Error Amplifier

The error amplifier in the HV9120 is a true low-power dif-

ferential input operational amplifier intended for around-the-

amplifier compensation. It is of mixed CMOS-bipolar con-

struction: A PMOS input stage is used so the common-mode

range includes ground and the input impedance is very high.

This is followed by bipolar gain stages which provide high

gain without the electrical noise of all-MOS amplifiers. The

amplifier is unity-gain stable.

Current Sense Comparators

The HV9120 uses a true dual-comparator system with in-

dependent comparators for modulation and current limiting.

This allows the designer greater latitude in compensation

design, as there are no clamps (except ESD protection) on

the compensation pin. Like the error amplifier, the compara-

tors are of low-noise BiCMOS construction.

Remote Shutdown

The SHUTDOWN and RESET pins of the HV9120 can be

used to perform either latching or non-latching shutdown of

a converter as required. These pins have internal current

source pull-ups so they can be driven from open-drain logic.

When not used, they should be left open or connected to

VDD.

Output Buffer

The output buffer of the HV9120 is of standard CMOS con-

struc-tion (P-channel pull-up, N-channel pull-down). Thus the

body-drain diodes of the output stage can be used for spike

clipping if necessary, and external Schottky diode clamping

of the output is not required.

SHUTDOWN

RESET

Output

H

H

Normal operation

H

H → L

Normal operation, no change

L

H

Off, not latched

L

L

Off, latched

L → H

L

Off, latched, no change

Truth Table

Shutdown Timing Waveforms

50%

t

D

1.5V

SENSE

0

t

SD

50%

90%

90%

VDD

SHUTDOWN

0

t

LW

50%

50%

t

SW

50%

50%

t

RW

50%

t

t

t

VDD

SHUTDOWN

0

VDD

RESET

0

VDD

OUTPUT

0

VDD

OUTPUT

0