FEDL610Q178FULL-01

ML610Q178

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BLOCK DIAGRAM

Figure 1-1 is a block diagram of the ML610Q178.

Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding port.

Program

Memory

（

Flash）

128Kbyte

RAM

4096byte

Interrupt

Controller

CPU (nX-U8/100) Large Model

Timing

Controller

EA

SP

Instruction

Decoder

BUS

Controller

Instruction

Register

TBC

INT

4

INT

6

8bit Timer

×

6

GPIO

NMI

P20 to P23

INT

5

P50 to P53

Data-bus

TEST0

RESET_N

OSC

POWER

RESET &

TEST

ALU

EPSW1～3

PSW

ELR1～3

LR

ECSR1～3

DSR/CSR

PC

GREG

0～15

OUTCLK*

UART

RXD0*

TXD0*

INT

2

LSCLK*

P40 to P43

On-Chip

ICE

P00 to P03

SSIO

SCK0*

SIN0*

SOUT0*

INT

2

WDT

INT

10bit-ADC

AIN0 to AIN15

*3

OSC0*

1

INT

INT

1

SDA*

1

SCL*

1

PWM

INT

2

PWM4*

1

PWM5*

1

LCD

Driver

COM0 to COM3

SEG0 to SEG7

LCD

Drive Voltage

XT0

XT1

P60 to P67

*3

P90 to P93

BLD

PW45EV0*

1

P30 to P33

*3

INT

1

P10 to P11

P34 to P36

OSC1*

TEST1_N

P44 to P47

*3

SEG8 to SEG39

*2

PW45EV1*

1

PC0 to PC7

*2

PD0 to PD7

*2

PE0 to PE7

*2

PF0 to PF7

*2

*

*

*