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ML610Q111 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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3 / 26 page FEDL610Q111-01 ML610Q111/ML610Q112 3/26 Analog comparator − 2ch ch0: Allows comparison of the voltage level of the two external pins or comparison of one external pin and internal reference voltage level. ch1: Allows comparison of one external pin and internal reference voltage level − Input common mode voltage range : V DD = 0.1V to VDD - 1.5V − Internal reference voltage : 0.1-0.8V (Selectable in 50mV increments) − Hysteresis (Comparator0 only): 20mV(Typ.) − Allows selection of with/without interrupt sampling and interrupt edge. General-purpose ports (GPIO) − Input/output port 15ch (ML610Q111) 25ch (ML610Q112) Reset − Reset by the RESET_N pin − Reset by power-on detection − Reset by the watchdog timer (WDT) 2nd overflow − Reset by the voltage level supervisor (VLS) function: Selectable by software Voltage level supervisor (VLS) − 2ch ch0: It can be used for voltage level detection reset ch1: It can be used for voltage level detection interrupt − Judgment accuracy: ±3.0% (Typ.) Clock − Low-speed clock: Built-in RC oscillation (32.768kHz) − High-speed clock: Built-in PLL oscillation (16.384MHz) High-speed external clock (max. 8.192MHz) Maximum CPU clock is 8.192MHz. − Selection of high-speed clock mode by software: Built-in PLL oscillation External clock Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states) − STOP mode: Stop of oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock). − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. |
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