NOIV1SN5000A-QDC datasheet(7/71 Pages) ONSEMI

Part #	NOIV1SN5000A-QDC

Description	VITA 5000 5.3 Megapixel 75 FPS Global Shutter CMOS Image Sensor

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NOIV1SN5000A

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OVERVIEW

Figure 4 gives an overview of the major functional blocks

of the sensor respectively. The system clock is received by

the CMOS clock input. A PLL generates the intenal, high

speed, clocks, which are distributed to the other blocks.

Optionally, the sensor can also accept a high speed LVDS

clock, in which case the PLL will be disabled.

The sequencer defines the sensor timing and controls the

image core. The sequencer is started either autonomously

(master mode) or on assertion of an external trigger (slave

mode). The image core contains all pixels and readout

circuits. The column structure selects pixels for readout and

performs correlated double sampling (CDS) or double

sampling (DS). The data comes out sequentially and is fed

into the analog front end (AFE) block. The programmable

gain amplifier (PGA) of the AFE adds the offset and gain.

The output is a fully differential analog signal that goes to the

ADC, where the analog signal is converted to a 10-bit data

stream. Depending on the operating mode, eight or ten bits

are fed into the data formatting block. This block adds

synchronization information to the data stream based on the

frame timing. The data then goes to the low voltage serial

(LVDS) interface block which sends the data out through the

I/O ring.

On-chip programmability is achieved through the Serial

Peripheral Interface (SPI). See the Register Map on page 44

for register details.

A bias block generates bias currents and voltages for all

analog blocks on the chip. By controlling the bias current,

the speed-versus-power of each block can be tuned. All

biasing programmability is contained in the bias block.

The sensor can automatically control exposure and gain

by enabling the automatic exposure control block (AEC).

This block regulates the integration time along with the

analog and digital gains to reach the desired intensity.

Figure 4. Block Diagram

Pixel Array

(2592x2048)

Analog Front End (AFE)

Data Formatting

Serializers & LVDS Interface

LVDS Clock

Input

LVDS Interface

16 Analog channels

16 x 10 bit

Digital channels

8 LVDS Channels

1 LVDS Sync Channel

1 LVDS Clock Channel

8 x 10 bit

Digital channels

Column Structure

Image Core Bias

Image Core

Automatic

Exposure

Control

(AEC)

Clock

Distribution

CMOS Clock

Input

LVDS Receiver

PLL

Control &

Registers

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NOIV1SN5000A-QDC Datasheet(PDF) 7 Page - ON Semiconductor

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