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PI6C10804 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C10804 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
1 / 7 page 1 PS8822G 10/07/09 Pin Description Pin Name Description BUF_IN Input CLK [0:3] Outputs GND Ground VDD Power OE Output Enable 1 2 3 4 CLK1 VDD GND CLK3 8 7 6 5 BUF_IN CLK0 OE CLK2 Pin Configuration Block Diagram Features • High-speed, low-noise, non-inverting 1:4 buffer • Maximum Frequency up to 180 MHz • Low output skew < 70ps (1.8V, 2.5V), <100ps (1.5V) • Low propagation delay < 3.0ns (1.8V, 2.5V), <3.5ns (1.5V) • Optimized duty cycle • 1.5V - 2.5V supply voltage • 3.3V Tolerant input clock • Packages (Pb-free & Green available): −8-pin SOIC (W) 1.5V/1.8V/2.5V, 180MHz, 1:4 Networking Clock Buffer PI6C10804 Description The PI6C10804 is a 1.5V to 2.5V high-speed, low-noise 1:4 non-inverting clock buffer. The key goal in designing the PI6C10804 is to target networking applications that require low- skew, low-jitter, and high-frequency clock distribution. Providing output-to-output skew as low as 70ps, the PI6C10804 is an ideal clock distribution device for synchronous systems. De- signing synchronous networking systems requires a tight level of skew from a large number of outputs. CLK2 CLK1 CLK0 BUF_IN CLK3 OE 09-0056 |
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