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ADC084S021 Datasheet(PDF) 6 Page - Texas Instruments |
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ADC084S021 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 27 page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 Track Hold Power Up Track Hold b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 9 10 DB5 DB4 DB3 DB2 DB1 DB0 DB5 DB4 DB3 DIN DOUT Power Up SCLK CS Power Down Control register Control register DB7 DB6 DB7 DB6 ADC084S021 SNAS279E – APRIL 2005 – REVISED MARCH 2013 www.ti.com ADC084S021 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 0.8 MHz to 3.2 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 50 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (1) Units VA = +3.0V tCSU Setup Time SCLK High to CS Falling Edge (2) 10 VA = +5.0V −0.5 VA = +3.0V +4.5 tCLH Hold time SCLK Low to CS Falling Edge (2) 10 ns (min) VA = +5.0V +1.5 VA = +3.0V +4 tEN Delay from CS Until DOUT active 30 ns (max) VA = +5.0V +2 VA = +3.0V +16.5 tACC Data Access Time after SCLK Falling Edge 30 ns (max) VA = +5.0V +15 tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min) tH Data Valid SCLK Hold Time +3 10 ns (min) tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) VA = +3.0V 1.7 Output Falling VA = +5.0V 1.2 tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max) VA = +3.0V 1.0 Output Rising VA = +5.0V 1.0 (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). (2) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed. Timing Diagrams Figure 2. ADC084S021 Operational Timing Diagram 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC084S021 |
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