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ADC10732 Datasheet(PDF) 7 Page - Texas Instruments |
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ADC10732 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 34 page ADC10731, ADC10732, ADC10734, ADC10738 www.ti.com SNAS081D – MAY 1999 – REVISED MARCH 2013 Electrical Characteristics (continued) The following specifications apply for V + = AV+ = DV+ = +5.0 V DC, VREF+ = 2.5 VDC, VREF− = GND, VIN− = 2.5V for Signed Characteristics, VIN− = GND for Unsigned Characteristics and fCLK = 2.5 MHz unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C. (1)(2)(3)(4) Units Parameter Test Conditions Typ(5) Limits(6) (Limits) DIGITAL AND DC CHARACTERISTICS VIN(1) Logical “1” Input Voltage V+ = 5.5V 2.0 V (min) VIN(0) Logical “0” Input Voltage V+ = 4.5V 0.8 V (max) IIN(1) Logical “1” Input Current VIN = 5.0V 0.005 +2.5 μA (max) IIN(0) Logical “0” Input Current VIN = 0V −0.005 −2.5 μA (max) V+ = 4.5V, IOUT = −360 2.4 V (min) μA VOUT(1) Logical “1” Output Voltage V+ = 4.5V, IOUT = −10 μA 4.5 V (min) VOUT(0) Logical “0” Output Voltage V+ = 4.5V, IOUT = 1.6 mA 0.4 V (min) VOUT = 0V −0.1 −3.0 μA (max) IOUT TRI-STATE Output Current VOUT = 5V +0.1 +3.0 μA (max) +ISC Output Short Circuit Source Current VOUT = 0V, V + = 4.5V −30 −15 mA(min) −ISC Output Short Circuit Sink Current VOUT= V + = 4.5V 30 15 mA (min) CS = HIGH, Power Up 0.9 1.3 mA (max) CS = HIGH, Power Down 0.2 0.4 mA (max) ID+ Digital Supply Current (10) CS = HIGH, Power Down, 0.5 50 μA (max) and CLK Off CS = HIGH, Power Up 2.7 6.0 mA (max) IA+ Analog Supply Current (10) CS = HIGH, Power Down 3 15 μA (max) VREF+ = +2.5V and IREF Reference Input Current 0.6 mA (max) CS = HIGH, Power Up AC CHARACTERISTICS 3.0 2.5 MHz fCLK Clock Frequency 5 (max) kHz (min) 40 %(min) Clock Duty Cycle 60 %(max) Clock 12 12 Cycles tC Conversion Time 5 5 μs (max) Clock 4.5 4.5 Cycles tA Acquisition Time 2 2 μs (max) 14 30 ns (min) CS Set-Up Time, Set-Up Time from Falling Edge of CS to tSCS (1 tCLK (1 tCLK Rising Edge of Clock (max) − 14 ns) − 30 ns) DI Set-Up Time, Set-Up Time from Data Valid on DI to tSDI 16 25 ns (min) Rising Edge of Clock DI Hold Time, Hold Time of DI Data from Rising Edge of tHDI 2 25 ns (min) Clock to Data not Valid on DI DO Access Time from Rising Edge of CLK When CS is tAT 30 50 ns (min) “Low” during a Conversion DO or SARS Access Time from CS , Delay from Falling tAC 30 70 ns (max) Edge of CS to Data Valid on DO or SARS Delay from Rising Edge of Clock to Falling Edge of SARS tDSARS 100 200 ns (max) when CS is “Low” (10) The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low = 0V and logic High = 5V). TTL levels increase the current, during power down, to about 300 μA. Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC10731 ADC10732 ADC10734 ADC10738 |
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