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ADC121S625CIMM Datasheet(PDF) 6 Page - Texas Instruments |
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ADC121S625CIMM Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 31 page  DOUT SCLK CS tCYC tCONV MSB tCHLD tACQ tCL tCH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 tCSCR tCFCS HI-Z HI-Z tEN NULL DB10 DB9 DB8 DB7 DB6 DB11 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 NULL DB8 tCDV tDIS POWER DOWN ADC121S625 SNAS294B – MAY 2005 – REVISED MARCH 2013 www.ti.com ADC121S625 Converter Electrical Characteristics (1) (continued) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 to 3.2 MHz, fIN = 20 kHz, CL = 100 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Units Symbol Parameter Conditions Typical Limits (2) Normal Operation 16 SCLK cycles tCYC Throughput Time SCLK cycles Short Cycled 14 (min) fRATE Throughput Rate 200 ksps (max) tAD Aperture Delay 6 ns ADC121S625 Timing Specifications (1) The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 MHz to 3.2 MHz, CL = 100 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits Units tCFCS SCLK Fall toCS Fall 0 ns (min) tCSCR CS Fall to SCLK Rise See (2) 0 ns (min) tCHLD SCLK Fall to Data Change Hold Time See (2) 10 ns (min) tCDV SCLK Fall to Next DOUT Valid 38 100 ns (max) tDIS Rising Edge of CS To DOUT Disabled 38 50 ns (max) tEN 2nd SCLK Fall after CS Fall to DOUT Enabled 6 50 ns (max) tCH SCLK High Time 42 60 ns (min) tCL SCLK Low Time 42 60 ns (min) tr DOUT Rise Time 5 50 ns (max) tf DOUT Fall Time 13 50 ns (max) (1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis. (2) Clock should be in low when CS is asserted, as indicated by the tCSCR and tCFCS specifications. Timing Diagrams Figure 2. ADC121S625 Single Cycle Timing Diagram 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC121S625 |
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