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TLV2545IDG4 Datasheet(PDF) 9 Page - Texas Instruments |
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TLV2545IDG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 33 page TLV2541, TLV2542, TLV2545 2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN SLAS245E −MARCH 2000 − REVISED APRIL 2010 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VDD 2.7 3.3 5.5 V Positive external reference voltage input, VREFP (see Note 1) 2 VDD V Analog input voltage (see Note 1) 0 VDD V High level control input voltage, VIH 2.1 V Low-level control input voltage, VIL 0.6 V Setup time, CS falling edge before first SCLK falling edge, VDD = REF = 4.5 V 40 ns Setup time, CS falling edge before first SCLK falling edge, tsu(CSL-SCLKL) VDD = REF = 2.7 V 70 ns Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL) 5 ns Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH) (TLV2541 only) 0.5 7 SCLKs Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLV2541 only) 0.35 SCLKs Hold time, FS high after SCLK falling edge, th(SCLKL-FSL) (TLV2541 only) 0.65 SCLKs Pulse width CS high time, tw(H_CS) 100 ns Pulse width FS high time, tw(H_FS) (TLV2541 only) 0.75 SCLKs SCLK cycle time, VDD = 3.6 V to 2.7 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 90 10000 ns SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 50 10000 ns Pulse width low time, tw(L_SCLK) 0.4 0.6 SCLK Pulse width high time, tw(H_SCLK) 0.4 0.6 SCLK Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion time, tc) 0.05 μs Active CS cycle time to reset internal MUX to AIN0, t(reset cycle) (TLV2542 only) 4 7 SCLKs Delay time delay from CS falling edge to SDO valid t VDD = REF = 4.5 V, 25-pF load 40 ns Delay time, delay from CS falling edge to SDO valid, td(CSL-SDOV) VDD = REF = 2.7 V, 25-pF load 70 ns Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV) VDD = REF = 4.5 V, 25-pF load 1 ns Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV) (TLV2541 only) VDD = REF = 2.7 V, 25-pF load 1 ns Delay time, delay from SCLK rising edge to SDO valid, VDD = REF = 4.5 V, 25-pF load 11 ns Delay time, delay from SCLK rising edge to SDO valid, td(SCLKH-SDOV) VDD = REF = 2.7 V, 25-pF load 21 ns Delay time, delay from 17th SCLK rising edge to SDO 3-state, VDD = REF = 4.5 V, 25-pF load 30 ns Delay time, delay from 17th SCLK rising edge to SDO 3 state, td(SCLK17H-SDOZ) VDD = REF = 2.7 V, 25-pF load 60 ns Conversion time, tc Conversion clock = internal oscillator 2.1 2.6 3.5 μs Sampling time, t(sample) See Note 2 300 ns Operating free air temperature T TLV2541/2/5C 0 70 °C Operating free-air temperature, TA TLV2541/2/5I −40 85 °C NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied to GND convert as all zeros(000000000000). 2. Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 kΩ), where RS is the source output impedance. |
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