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ADS1675 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS1675 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 38 page  CLK DRDY t LSCLK SCLK EXTERNAL t LDRPW t CLKDR t CSSC t CSFDO t SPW t SPW t LDOPD t CSRDO DOUT CS (1) MSB LSB t CLK t LSCLKDR Hi-Z START DRDY CLK t START_CLKR t SETTLE t START t CLKDR ADS1675 www.ti.com SBAS416D – DECEMBER 2008 – REVISED AUGUST 2010 (3) CS may be tied low. Figure 4. Low-Speed Mode Data Retrieval Timing with External SCLK (SCLK_SEL = 1) TIMING REQUIREMENTS: External SCLK At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V. SYMBOL DESCRIPTION MIN TYP MAX UNIT tCLK CLK period (1/fCLK) 31.25 ns tCLKDR CLK to DRDY delay 23 29 ns tLDRPW DRDY pulse width 1 tCLK tCSSC CS active low to first Shift Clock (setup time) 5 ns tLSCLK SCLK period (1/fSCLK) 25 ns tSPW SCLK high or low pulse width 12 ns tLDOPD Rising edge of SCLK to new valid data output (propagation delay) 10.5 15 ns tLSCLKDR Setup time of DRDY rising after SCLK falling edge 3 tCLK tCSRDO CS rising edge to DOUT 3-state 8 ns Figure 5. START Timing TIMING REQUIREMENTS: START At TA = –40°C to +85°C, and DVDD = 2.85V to 3.15V. SYMBOL DESCRIPTION MIN TYP MAX UNIT tSTART_CLKR Setup time, rising edge of START to rising edge of CLK 0.5 tCLK tSTART Start pulse width 2 tCLK Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS1675 |
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