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ADS1281 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS1281 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 51 page SCLK DIN DOUT t SCLK t SPWH t SCDL t DIST t DIHD t SPWL t SCDL t DOHD t DOPD ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com TIMING DIAGRAM TIMING REQUIREMENTS At TA = –40°C to +85°C and DVDD = 1.65V to 3.6V, unless otherwise noted. PARAMETER DESCRIPTION MIN MAX UNITS tSCLK SCLK period 2 16 1/fCLK tSPWH, L SCLK pulse width, high and low(1) 0.8 10 1/fCLK tDIST DIN valid to SCLK rising edge: setup time 50 ns tDIHD Valid DIN to SCLK rising edge: hold time 50 ns tDOPD SCLK falling edge to valid new DOUT: propagation delay(2) 100 ns tDOHD SCLK falling edge to DOUT invalid: hold time 0 ns Final SCLK rising edge of command to first SCLK rising edge for register read/write tSCDL 24 1/fCLK data. (Also between consecutive commands.) (1) Holding SCLK low for 64 DRDY falling edges resets the SPI interface. (2) Load on DOUT = 20pF || 100k Ω. 6 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 |
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