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ADC10D020 Datasheet(PDF) 9 Page - Texas Instruments

Part # ADC10D020
Description  ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC10D020 Datasheet(HTML) 9 Page - Texas Instruments

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ADC10D020
www.ti.com
SNAS143D – SEPTEMBER 2001 – REVISED MARCH 2013
AC Electrical Characteristics
OS = High (Parallel Mode)
The following specifications apply for VA = +3.0 VDC, VD = +3.0 VDC, VDR = +3.0VDC, VREF = 1.0 VDC, GAIN = OF = 0V, OS =
3.0V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 20 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset
corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C
(1)
Units
Symbol
Parameter
Conditions
Typical (2)
Limits (3)
(Limits)
fCLK1
Maximum Clock Frequency
30
20
MHz (min)
fCLK2
Minimum Clock Frequency
1
MHz
30
% (min)
Duty Cycle
50
70
% (max)
Pipeline Delay (Latency)
2.5
Conv Cycles
tr, tf
Output Rise and Fall Times
7
ns
toc
OC Pulse Width
10
ns
Output Delay from CLK Edge to Data
tOD
15
21
ns (max)
Valid
tDIQ
I/Q Output Delay
13
ns
tAD
Sampling (Aperture) Delay
2.4
ns
tAJ
Aperture Jitter
<10
ps (rms)
tVALID
Data Valid Time
43
ns
Overrange Recovery Time
Differential VIN step from 1.5V to 0V
50
ns
PD Low to 1/2 LSB Accurate Conversion
tWUPD
<1
ms
(Wake-Up Time)
STBY Low to 1/2 LSB Accurate
tWUSB
800
ns
Conversion (Wake-Up Time)
(1)
The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.
However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. See Figure 2
(2)
Typical figures are at TJ = 25°C, and represent most likely parametric norms.
(3)
Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is ensured only at VREF = 1.0V and a clock duty
cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are
performed and limits specified with clock low and high levels of 0.3V and VD − 0.3V, respectively.
Figure 2.
Copyright © 2001–2013, Texas Instruments Incorporated
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