3

2

4

6

1

GND

VIN

CS

SCLK

SDO

5

1

2

4

5

6

14

15

CS

SCLK

SDO

0

0

0

D11

D10

D3

D2

13

D1

D0

16

t

d1

t

h1

1/throughput

b

a

ADS7886

SLAS492A – SEPTEMBER 2005 – REVISED NOVEMBER 2009

www.ti.com

DEVICE INFORMATION

SOT23/SC70 PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

1

–

Power supply input also acts like a reference voltage to ADC.

GND

2

–

Ground for power supply, all analog and digital signals are referred with respect to this pin.

VIN

3

I

Analog signal input

SCLK

4

I

Serial clock

SDO

5

O

Serial data out

CS

6

I

Chip select signal, active low

NORMAL OPERATION

The cycle begins with the falling edge of CS. This point is indicated as a in Figure 1. With the falling edge of CS,

the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion

is in progress. The data word contains 4 leading zeros, followed by 12-bit data in MSB first format.

The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until

the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. On the 16th

falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge of SCLK.

The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is

indicated by b in Figure 1.

CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by

necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase

and no valid data is available in the next cycle. (Also refer to power down mode for more details.) CS going high

any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.

high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from

another circuit with different supply levels. Also, this relaxes the restriction on power up sequencing. However,

Figure 1. Interface Timing Diagram

6

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