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ADS62P25IRGCRG4 Datasheet(PDF) 1 Page - Texas Instruments |
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ADS62P25IRGCRG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 78 page ADS62P24, ADS62P25 ADS62P22, ADS62P23 www.ti.com SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS62P24, ADS62P25, ADS62P22, ADS62P23 1 FEATURES • High Definition Video • Medical Imaging • Maximum Sample Rate: 125 MSPS • Radar Systems • 12-Bit Resolution with No Missing Codes • 95 dB Crosstalk DESCRIPTION • Parallel CMOS and DDR LVDS Output Options ADS62P2X is a dual channel 12-bit A/D converter • 3.5 dB Coarse Gain and Programmable Fine family with maximum sample rates up to 125 MSPS. Gain up to 6 dB for SNR/SFDR Trade-Off It combines high performance and low power consumption in a compact 64 QFN package. Using • Digital Processing Block with: an internal sample and hold and low jitter clock – Offset Correction buffer, the ADC supports high SNR and high SFDR at – Fine Gain Correction, in Steps of 0.05 dB high input frequencies. It has coarse and fine gain options that can be used to improve SFDR – Decimation by 2/4/8 performance at lower full-scale input ranges. – Built-in and Custom Programmable 24-Tap Low-/High-/Band-Pass Filters ADS62P2X includes a digital processing block that consists of several useful and commonly used digital • Supports Sine, LVPECL, LVDS, and LVCMOS functions such as ADC offset correction, fine gain Clocks and Amplitude Down to 400 mVPP correction (in steps of 0.05 dB), decimation by 2,4,8 • Clock Duty Cycle Stabilizer and in-built and custom programmable filters. By • Internal Reference; Supports External default, the digital processing block is bypassed, and Reference also its functions are disabled. • 64-QFN Package (9mm × 9mm) Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P2X • Pin Compatible 14-Bit Family (ADS62P4X) includes internal references while traditional reference pins and associated decoupling capacitors APPLICATIONS have been eliminated. Nevertheless, the device can • Wireless Communications Infrastructure also be driven with an external reference. The device is specified over the industrial temperature range • Software Defined Radio ( –40°C to 85°C). • Power Amplifier Linearization • 802.16d/e • Test and Measurement Instrumentation Table 1. ADS62P2X Performance Summary ADS62P25 ADS62P24 ADS62P23 ADS62P22 Fin = 10 MHz (0 dB gain) 88 92 93 94 SFDR, dBc Fin = 190 MHz (3.5 dB gain) 84 86 87 85 Fin = 10 MHz (0 dB gain) 71 71.3 71.5 71.5 SINAD, dBFS Fin = 190 MHz (3.5 dB gain) 69.5 69.5 69.7 69.2 Analog power, mW 799 710 594 515 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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